As the density of large scale integrated circuits increases, it has been found necessary to use more than one level of metal interconnection between the transistor structures on the semiconductor chip. FIGS. 8a through 8c show the interconnection point between the first level metal line 6' and a second level metal line 20' forming a via connection. In the prior art process for forming this structure, a first layer 6 of metal such as an alloy of aluminum, copper and silicon is deposited on either a silicon substrate 2 or a silicon dioxide layer 4 and, through photolithographic techniques, the metallized line 6' is delineated. This array of first level metal lines is then covered over by a layer of sputtered quartz 12, for example, which will serve as the insulating layer between the first and second level metal lines. Then a via hole is formed in the quartz layer 12 over a section of the first level metal line 6' where an electrical interconnection between the first level and second level metal lines is designed. This is followed by the deposition of a second level metal layer 20, which, through photolithographic processes will have a second level metal line 25 delineated therein which intersects the via hole and makes the desired electrical contact with the first level metal line. In the interest of density it is desired that the second metal line not be required to totally overlap the via hole. This would require the second metal line to be sufficiently wider than the via hole in order to allow for misalignment and other process tolerances. The prior art process for forming the second level metal line is to either use a wet etching technique employing phosphoric acid or a reactive ion etching technique employing carbon tetrachloride to etch the aluminum-copper second metal layer 20. The problem which confronts the prior art is that there is no reliable way to protect the first level metal layer 6' after the second level metal layer 20 is etched through to completion. Variations in the thickness of the second level metal layer 20 due to the tolerances therein, and variations in alignment and linewidth force the process parameters to be set to etch the thickest second level metal layer which will probably be encountered. Thus, for thin layers of second level metal, the first level metal layer 6' will be overetched at 26 and 26'. By overetching, the first level metal line 6', the current being conducted through that conductor line will have a higher density at the points of lower cross-sectional area, thereby contributing to overheating, electromigration phenomema, higher contact resistance due to current crowding, all of which contribute to a reduced reliability and reduced performance for the resulting large scale integrated circuit.